CORNERSTONE users are invited to submit designs to the sixth call. The platform is 220 nm Si / 2 µm buried oxide (BOX) silicon-on-insulator (SOI). There will be 3 silicon etches of 70 nm (grating couplers), 120 nm (rib waveguides) and 220 nm (strip waveguides). In addition, there will be two layers for metal heaters (heater filaments and heater contact pads).
For the first time, a process design kit (PDK) has been made available using Luceda’s IPKISS software. To obtain a copy of the software and a license key, please contact Luceda by sending an email to support@lucedaphotonics.com, specifying that you require a license for CORNERSTONE PDK usage.
Access to this run is free of charge for UK research institutes (funded by EPSRC). Overseas universities and industrial companies can access this run with the following options:
The mask submission deadline is Friday 6th April 2018.
For more information, full design rules and quick reference design rules, please visit: www.cornerstone.sotonfab.co.uk/mpw-design-rules
For any queries, please contact cornerstone@soton.ac.uk